1. Field of the Invention
The present invention relates to a sense amplifier and a semiconductor memory device having the sense amplifier.
2. Description of Related Art
With improvement in a semiconductor technology, a semiconductor memory device in which increase in a chip area is suppressed and amount of memory is increased has been widely prevalent. A semiconductor memory device has a plurality of memory cells. Each memory cell stores one bit that is the minimum unit of information. For suppressing increase in the chip area and increasing the amount of memory, each memory cell has been miniaturized such that memory cells can be placed densely within a predetermined region.
It's often the case that amplitude of a signal output from the miniaturized memory cell is small. In order to amplify the signal having small amplitude, the semiconductor memory device such as a DRAM (Dynamic RAM) and an SRAM (Static RAM) is provided with a sense amplifier. The sense amplifier amplifies the small-amplitude signal read out from the memory cell to a level that a logic circuit outside of the semiconductor memory device can deal with.
In recent years, most of the semiconductor memory devices are provided with a sense amplifier having a differential amplifier circuit (hereinafter referred to as a “differential sense amplifier”). A current mirror type sense amplifier and a latch type sense amplifier are known as a typical differential sense amplifier. Such a differential sense amplifier generates an amplified signal by amplifying the signal read out from the memory cell based on a difference in voltage between a pair of two signal lines. In recent years, a power supply voltage of the semiconductor integrated circuit is lowered, and many semiconductor memory devices are provided with the latch type sense amplifier that can operate with a low power supply voltage, has no DC current path and thus enables low power consumption.
With regard to the sense amplifier installed in the semiconductor memory device, it is required to correctly read the memory cell data even if the difference in voltage between the two signal lines is small. Moreover, a high-speed operation is required. Furthermore, a small size and low power consumption are required. In order to configure a sense amplifier that can correctly read the memory cell data even if the difference in voltage between the two signal lines is small, it is known to be effective to reduce an offset voltage. To reduce the offset voltage of the sense amplifier is also effective for speeding up the operation, because no error read occurs when an operating start time of the sense amplifier is made earlier. A technique of reducing the offset voltage of the sense amplifier is described, for example, in Japanese Laid-Open Patent Application JP-2003-173685 and Japanese Laid-Open Patent Application JP-2002-083497.
In general, the offset voltage of the sense amplifier can be expressed as synthesis of a systematic offset component and a random offset component. Here, the systematic offset is a phenomenon that the offset voltages of all sense amplifiers shift to the same one side due to circuit design asymmetry between differential pairing. On the other hand, the random offset is caused by various factors mainly due to manufacturing variability (e.g. variation in the number of ions injected, variation in a size of a fabricated gate electrode, and the like) and takes a random value with respect to each sense amplifier. A frequency distribution of the random offset voltages for a large number of sense amplifiers is approximated by the Gaussian distribution.
FIG. 1 is a circuit diagram showing a configuration of a latch type sense amplifier 101 disclosed in Japanese Laid-Open Patent Application JP-2003-173685. In the sense amplifier 101, bit lines constituting a complementary bit line pair connected to a memory cell are respectively connected to gates of a NMOS (n-channel MOS) transistor T9 and a NMOS transistor T11. Moreover, a pair of a PMOS (p-channel MOS) transistor T5 and a PMOS transistor T6 and a pair of a NMOS transistor T10 and a NMOS transistor T12 are so connected as to form a latch circuit and to achieve the amplification function. The transistors constituting the transistor pair are symmetrically placed in order to prevent imbalance between the transistors due to difference in pattern. Also, those transistors are typically designed to be larger in size as compared with transistors used in a normal logic circuit in order to reduce random variation in device characteristics.
A PMOS transistor T4 and a PMOS transistor T7 are precharge transistors used for setting internal nodes Na and Nb of the sense amplifier 101 to high potential prior to the amplification operation. A PMOS transistor T8 is an equalizer transistor used for securing potential equilibrium between the internal nodes Na and Nb of the sense amplifier 101 prior to the amplification operation.
A NMOS transistor T13 functions as an activation switch for operating the sense amplifier. When the NMOS transistor T13 is turned ON, a small potential difference input to the NMOS transistor T9 and the NMOS transistor T11 is amplified to the power supply voltage and then output to the outside of the sense amplifier through an inverter Iv6.
As shown in FIG. 1, the latch type sense amplifier 101 further has an inverter Iv5 whose output is open and which is symmetrically placed with respect to the inverter Iv6. The inverter Iv5 secures layout symmetry and thereby suppresses occurrence of the systematic offset due to imbalance in electrostatic capacitance between the differential pairing. In the case of the latch type sense amplifier 101 shown in FIG. 1, the capacitance balance is secured by placing the inverter Iv5 that has the same input capacitance as of the inverter Iv6.
Japanese Laid-Open Patent Application JP-2002-083497 discloses a technique related to a semiconductor integrated circuit and intended to reduce influence of the offset voltage when a voltage depending on a potential difference between the first and second signal lines is amplified and output. According to the technique, a bit line voltage is adjusted depending on an offset voltage of a flip-flop and thereby a voltage depending on a potential difference between bit lines is output without being influenced by the offset voltage of the flip-flop.
The inventor of the present application has recognized the following points. In the sense amplifier applied to the semiconductor memory device, it is important to design the offset voltage as small as possible. As described above, to use a large element is preferable for reducing the random offset caused by the manufacturing variability. Moreover, in order to reduce the systematic offset, it is preferable to design the layout as symmetric as possible between the differential pairing.
According to the technique described in Japanese Laid-Open Patent Application JP-2003-173685, for example, the inverter (Iv5) that is a dummy element irrelevant to a logic operation is placed for reducing the imbalance in capacitance between the differential pairing. Even in this case, however, the variation in device characteristics due to variation in a size of a fabricated gate electrode, variation in the number of ions injected, non-uniformity of manufacturing conditions and the like is inevitable in principle. Thus, there is a limit to the reduction of the offset voltage of the sense amplifier. In the case of Japanese Laid-Open Patent Application JP-2002-083497 where the bit line voltage is adjusted depending on the offset voltage of the flip-flop, high-speed operation is difficult to achieve, which is disadvantageous.